1. Field of the Invention
The present invention relates to wireless receivers, and, in particular, to rake receivers for processing a signal that has been subjected to a multi-path channel.
2. Description of the Related Art
When a signal travels through a real-world environment, it often reaches a receiver by multiple paths. These paths occur as a result of the signal reflecting, diffracting, and scattering from various elements in the environment, e.g., mountains, trees, and buildings. Multi-path components are essentially time-delayed variants of a single signal. While, in some applications, these multiple components may result in interference, e.g., ghosting on the display of an analog television receiver, Code Division Multiple Access (CDMA) systems intentionally make use of these multiple components.
The basic principle of CDMA systems is orthogonal coding, whereby, instead of assigning specific frequencies or time slots to each user of a system, the users are distinguished from one another by assigning codes. The codes fulfill the same role as frequency or time in frequency- or time-division systems, i.e., to keep the signals for different users from interfering with one another. In orthogonal spreading, a symbol is XOR-multiplied by a defined bit sequence called a code. If the code length is n bits, each symbol is transformed to n so-called chips. The resulting chip rate, i.e., the number of bits per second (chips per second) used in the spreading signal, is n times the original symbol rate (number of symbols per second). For example, the spreading code 1111 has a length, also called a spreading factor (SF) or Orthogonal Variable Spreading Factor (OVSF), of four. A single 1 will be spread to the sequence 0000 (1 XOR'ed with 1 gives 0), and a single 0 will be spread to the sequence 1111. In general, codes are not arbitrarily chosen, but rather, selected according to certain mathematical rules that provide sets of codes that are orthogonal to each other. Orthogonal codes have no correlation. Consequently, signals spread with codes that are orthogonal to each other do not interfere with one another. For a single connection, input data is spread with a particular code at the transmitter end. To recover the data, the same orthogonal code is used at the receiver end to despread the signal.
In the Wideband CDMA (WCDMA) standard, data symbols are spread using high-frequency bit sequences that are specifically selected so as to have properties that allow the resulting signal to be distinguished from a delayed version of itself. This property makes it possible to receive signals from a set of component paths with different delays and combine them, resulting in improved reliability and performance. A rake receiver carries out this method by employing several correlators, each referred to as a finger. A rake receiver takes data from a digital radio front-end after conversion down to a baseband sample rate and despreads the signal down to the symbol rate. Since the signal from the user can take multiple paths to the receiver, the fingers of the receiver operate such that the resulting outputs can be combined to form one signal at the symbol rate. Thus, the system takes advantage of the multiple paths to achieve a higher performance than a single despreader, resulting in increased signal-to-noise ratio at the receiver, improved receive signal strength, and decreased fading due to poor channel quality.
Referring now to FIG. 1, a block diagram illustrating the structure of an exemplary prior-art rake receiver 100 is provided. As shown, rake receiver 100 has four identical fingers 101-0 to 101-3, each of which collects energy for a particular multi-path component of the received signal and then compensates for the delay of that multi-path component. During every chip period, each of fingers 101-0 to 101-3 handles a different data sample from the input multi-path stream. The input data sequence is typically over-sampled (e.g., 8×, which means there can be 8 samples in every chip period). Each finger represents one multi-path component and will start to process its respective data sample at a different time, since the multi-path components have different delays.
The first finger 101-0 has a despreader/descrambler 102-0, a time controller 103-0, a code generator 104-0, a delay compensator 105-0, and a multiplier 106-0. Time controller 103-0 provides a clock signal to control the timing of the operations performed by despreader/descrambler 102-0 and code generator 104-0.
In addition to despreading, receiver 100 also performs descrambling operations on the signal to account for the signal having been scrambled at the transmitter. Scrambling is typically performed using a pseudorandom noise (PN) code sequence, which results in a sequence appearing as random noise to a receiver that does not have the identical code sequence. Accordingly, code generator 104-0 produces a spreading sequence and a descrambling sequence, one bit per chip, and provides these sequences to despreader/descrambler 102-0. Despreader/descrambler 102-0 (i) receives the input stream signal, the clock signal from time controller 103-0, and the spreading and descrambling sequences from code generator 104-0, (ii) demodulates the multi-path signal by performing the appropriate despreading, descrambling, filtering (to remove noise), and possibly other operations, and (iii) provides an output signal to delay compensator 105-0.
Another operation performed by receiver 100 is deskewing the signal. Deskewing accounts for each path in the propagation channel imposing a different time delay on the signal by aligning the despread signals the multiple fingers in time. Delay compensator 105-0 deskews the demodulated signal based on information from channel configuration circuitry (not shown) and provides the deskewed signal to multiplier 106-0.
Multiplier 106-0 performs channel correction by multiplying the value of each of the de-spread symbols by the corresponding weight coefficient W0 of the multi-path channel-estimation amplitude, which is provided by a channel estimator (not shown), and outputs the weighted signal.
Following this multiplication process, the symbol data is provided to combiner 107, which accumulates the corrected symbol data from all of fingers 101-0 to 101-3 and outputs a signal representing a clean symbol-rate sequence that can be used as a decision statistic by additional hardware (not shown).
The structure of each of the second finger 101-1, third finger 101-2, and fourth finger 101-3 is the same as that of the first finger 101-0, and fingers 101-0 to 101-3 all function in the same manner.
As can be seen in the exemplary rake receiver 100 of FIG. 1, due to the number of operations that it performs and the multiple instances of each operation necessitated by the plurality of fingers, the hardware of a typical rake receiver is relatively complex. Moreover, a typical rake receiver requires a large amount of hardware area and dissipates a relatively large amount of power because of its multiple fingers.
Turning now to FIG. 2, one solution to the problem of hardware size involves implementing a time-multiplexing scheme with a hardware engine that time-multiplexes among the finger components. As shown, rake receiver 200 has a rake finger block 201, a code generator 202, an address generator 203, a multiplexing information table 204, a table entry generator 205, a sampling buffer 206, and an output buffer 207. Instead of using a large number of (e.g., 16) physical rake fingers, rake receiver 200 uses rake finger block 201, which includes circuitry for a smaller number of physical rake fingers (e.g., 4), with each finger being time-multiplexed a number of (e.g., 4) times, so as to provide the larger number of logical rake fingers. A single code generator 202 supplies OVSF and scrambling code sequences to the fingers of block 201. These sequences are generated, in part, using address generator 203 and multiplexing information table 204, which table contains configuration information including the position of the desired subchip (here, a subchip is ¼ of a chip period) and a counter for storing code offsets for each logical finger. Table entry generator 205 generates the entries for multiplexing information table 204.
In operation, input samples from an A/D converter are received at and stored in sampling buffer 206 pending decoding by the appropriate logical fingers of finger block 201, and the resulting decoded symbols are provided to output buffer 207, which outputs the symbols to rate determination circuitry (not shown) and a Viterbi decoder (not shown). In this scenario, samples of all (in this case, four) of the multi-path components of the multi-path signal are processed in parallel during a single chip period.
In this prior-art time-multiplexing scheme, one chip period is divided into four subchip periods, with each finger being assigned a subchip period to process one data sample at a time, such that all fingers perform their processing within a single chip period. A higher clock rate may be required to guarantee that there will be enough clock cycles for all of the fingers to complete their respective demodulation tasks (i.e., despreading, descrambling, accumulating, and filtering) within a given chip period when data corresponding to a number of chips equal to the spread factor has been accumulated into symbol data. In this scheme, certain chip periods will experience heavy traffic (i.e., to fulfill all demodulation tasks), while others will have lighter traffic (e.g., despreading, descrambling, and accumulating only). Accordingly, the bandwidth usage may be uneven. Moreover, this implementation still typically involves the dissipation of substantial power due to the high-frequency clock rate.